1. Field of the Invention
The present invention relates to a display device using a liquid crystal display panel of an active matrix type or the like, in particular to a display device using a display panel in which capacitance elements are individually connected to a plurality of picture element electrodes.
2. Description of the Related Art
Single matrix type display panels, for example, in which a pair of light transmitting substrates sandwiching a liquid crystal layer therebetween are opposed to each other, a plurality of scanning electrodes are arranged on one of the pair of substrates and a plurality of display electrodes are arranged on the other of the pair of substrates so that they intersect each other, are suitable for enlarging the panels in size because of their simple constitution, so that they have been widely used. However, since such panels have a few problems regarding response and crosstalk, active matrix type display panels in which switching elements are individually connected to picture elements are used for image display means of apparatuses such as TV receivers and personal computers, in which images are moved fast and a high resolution is required.
FIGS. 10, 11 are block diagrams showing constitutions of display devices of the prior art. For the purpose of simplification, in both the figures, an active matrix type display panel 52 is presented in a 4.times.4 matrix form, namely 16 picture elements. The display devices, 51A, 51B shown in FIGS. 10, 11, respectively, have a similar constitution to each other, and therefore the parts corresponding to each other are represented by the same reference numerals. More specifically, the display devices 51A, 51B are constituted identically, excepting that the return circuits of capacitance elements CS are connected to a counter electrode driving circuit 56 in the prior art as shown in FIG. 10, and in the prior art as shown in FIG. 11 they are connected to a power supplying circuit 54L for scanning. Accordingly the following description will be mentioned in respect of the display device 51A shown in FIG. 10.
In the active matrix type display panel 52 (hereinafter described as "display panel"), a plurality of signal lines Y51-Y54 for scanning (when generically described, represented by a reference numeral Y) and a plurality of signal lines X51-X54 for displaying (when generically described, represented by a reference numeral X) are arranged to intersect each other on one of the pair of substrates confronting each other and sandwiching a liquid crystal layer therebetween, and in the portions where the signal lines for scanning (hereinafter described as "scanning signal lines") and the signal lines for displaying (hereinafter described as "display signal lines") intersect each other are arranged picture element electrodes p51-p66. On the other of the pair of substrates are arranged counter electrodes q51-q66 so that each of them is opposed to each of the picture element electrodes. In such a manner, 16 picture elements P51-P66 arranged in a 4.times.4 matrix form are formed.
When the picture elements, picture element electrodes, and counter electrodes are generically described, they are represented by the reference numerals P, p, and q, respectively. Further, the scanning signal lines Y are also called "line in the first row, the second row, . . . " in the arrangement direction and on the other hand, the display signal lines X are also called "line in the first column, the second column, . . . " in the arrangement direction. Additionally, although practically the counter electrodes are formed as one piece of electrode on the other substrate in all, each picture element P is equivalently represented as a condenser for the purpose of simplifying the description, and the counter electrodes q51-q66 are represented to be connected to a counter electrode driving line Lq. A counter electrode driving voltage VQ outputted from the counter electrode driving circuit 56 is applied to the counter electrodes q51-q66 via a counter electrode driving line Lq.
On the one substrate, switching elements SW51-SW66 (when generically described, represented by a reference numeral SW) realized by thin film transistors (TFTs) are formed together with capacitance elements CS51-CS66 (when generically described, represented by a reference numeral CS), in a manner such that the switching elements SW51-SW66 correspond to the picture elements P51-P66 in a one-to-one correspondence manner. The source of the switching element SW is connected to the display signal line X and the drain of the switching element SW is connected to the picture element electrode p, individually. The switching element SW is in ON-state when scanning signals VG51-VG54 of each line applied to the gate are at high levels, and in OFF-state when the scanning signals VG51-VG54 are at low levels. A scanning signal lines driving circuit 53 is so constituted that a shift register which shifts a pulse every horizontal scanning period, and a level shifter circuit which shifts to high- and low-level scanning power supply voltages VGH, VGL outputted from scanning power supply circuits 54H, 54L in accordance with the pulses of the shift register are built-in, and the scanning signals to be changed into a low and a high level signal within one horizontal scanning period are derived in the scanning signal lines Y51-Y54.
The capacitance elements CS51-CS66 (hereinafter described as "condenser") are formed on the one substrate in parallel with the formation of the switching elements SW, in order to control the dispersion of the capacity of each picture element P as a capacitive element, and minimize the voltage drop. One electrodes of each of condensers CS is individually connected to the picture element electrodes p, and the other electrodes (hereinafter described as "return circuits"), as shown in Japanese Unexamined Patent Publication JPA 64-91185 (1989), are connected to the scanning signal line Y in the next row on the substrate, adjacent to the row of the picture elements to whose electrodes p the one electrodes of the condensers are connected, excepting that the return circuits of condensers CS63-CS66 in the fourth row are connected to the counter electrode driving line Lq in common because of the lack of scanning signal line in the next row.
Display signals VS51-VS54 corresponding to image data are individually applied to the display signal lines X51-X54 via a display signal lines driving circuit. For example, when a high-level scanning signal VG51(H) is applied to the scanning signal line Y51, the switching elements SW51-SW54 in the first row are turned on, and the display signals VS51-VS54 are applied to the picture elements P51-P54 in the first row via the display signal lines X51-X54. The polarity of the display signal VS is inverted every horizontal scanning period by a so-called alternating-current-like inversion driving method, in order to prevent polarization of the picture elements and flicker in displaying, and besides the display signal VS has a waveform such that the inversion order is alternated every vertical scanning period.
FIGS. 12A-12I are waveform diagrams of each part of the display device 51A. In FIGS. 12A-12I, the parts corresponding to those in FIG. 10 are represented by the same reference numerals as those in FIG. 10. In FIGS. 12A-12I, the transverse axis indicates times and the vertical axis voltage or signal levels. A value of 63.5 .mu.S for a horizontal scanning period 1H and a value of 262.5H (H indicates one horizontal scanning period) for one vertical scanning period 1B are based on a NTSC mode which is a TV standard mode. A vertical scanning period 1B for one field begins at a time t1. Time periods T1-T4 indicate the scanning periods for the scanning lines Y51-Y54. In the waveform diagrams, the period after a finish time t8 of an ON period T.sub.on4 in the fourth row is considered as a vertical retrace interval on the basis of the 4.times.4 matrix.
FIGS. 12A-12D are waveform diagrams of scanning signals VG51-VG54 applied to the scanning signal lines Y51-Y54. The high-level periods of the scanning signals VG51-VG54 mean ON periods T.sub.on1 -T.sub.on4 of the switching elements SW in each row, and the levels are equal to the power supply voltage VGH of high level for scanning outputted from a power supply circuit 54H for scanning (hereinafter described as "scanning power supply circuit"). The reason why the waveforms pulsates every 1H has a relationship with the below-mentioned power supply voltage VGL for scanning (hereinafter described as "scanning power supply voltage").
FIG. 12E is the waveform diagram of the low-level scanning power supply voltage VGL outputted from the scanning power supply circuit 54L. The scanning power supply voltage VGL pulsates every 1H. This is because alternating-current-like inversion driving is caused by the connection of the return circuit of the condenser CS. The switching elements SW are set to be at low level which is enough to maintain the switching elements in OFF state.
FIG. 12F is the waveform diagram of the counter electrode driving voltage VQ derived from the counter electrode driving circuit 56. Since the counter electrode driving voltage VQ is applied to the counter electrode q of the picture element P, the polarity is inverted every horizontal scanning period 1H due to alternating-current-like like inversion driving, and the voltage is synchronized with the scanning power supply voltage VGL. Consequently, like the display device 51B shown in FIG. 11, the return circuits of the condensers CS63-CS66 in the fourth row may be connected to the scanning power supply circuit 54L in common without causing problems and therefore the return circuits are connected to either of the counter electrode driving line or the scanning power supply circuit 54L, depending on the circuit pattern of the substrate.
FIG. 12G shows the waveform of the display signal VS. The display signal VS is a inverse signal, the polarity of which is inverted every horizontal scanning period due to alternating-current-like inversion drive, and although the display signals VS51-VS54 for each column are applied to the display signal lines individually via the display signal lines driving circuit 55, the display signals VS are indicated by a waveform inverted at the same level.
FIGS. 12H, 12I show a drive voltage VD55 applied to the picture element P55 in the second row and a driving voltage VD63 applied to the picture element P63 in the fourth row, respectively. Since the switching element SW55 is turned on/off via the scanning signal 52, the driving voltage VD55 applied to the picture element P55 in the second row changes as shown in FIG. 12H. Additionally, since the switching element SW63 is turned on/off via the display signal VG54, the driving voltage VD63 applied to the picture element P63 in the fourth row changes as shown in FIG. 12I. Such changes apply also to the other picture elements (not shown).
Although the waveforms of the driving voltages VD55, VD63 synchronize with the changes due to alternating-current-like inversion drive and change with a constant amplitude in periods excluding periods T.sub.on2, T.sub.on4, on the driving voltage VD55, the level of a voltage VGC is superposed on the driving voltage VD55 in the scanning period in the next third row, as shown in FIG. 12H. This is because the return circuit of the condenser CS55 connected to the picture element P55 is connected to the scanning signal line Y53 in the next third row. Consequently, in accordance to the capacity ratio of the capacitance Cp of the picture element P to the capacitance Cs of the condenser CS, the partialized voltage VGC as shown in the following equation (1) is superposed on the driving voltage VD52 in a scanning period T3 when the scanning signal VG53 is at a high level. EQU VGC=Cs(VGH-VGL)/(Cs+Cp) (1)
Although a floating capacitance exists between the gate and drain of the switching element due to constitutional reasons of the TFT, the capacitance is small in comparison with the Cp, Cs, and accordingly neglected herein.
The voltage VGC is also superposed on driving voltages which are applied to picture elements (not shown) in the first row and the third row, at different positions. On the driving voltages of the picture elements P63-P66 in the fourth row, is not superposed the voltage VGC like the waveform of the driving voltage VD83 as representatively shown in FIG. 12I. This is because the return circuits of the condensers CS63-CS66 in the fourth row are connected to the counter electrode driving line Lq or the scanning power supply circuit 54L shown in FIG. 11, unlike those in the other rows. For this reason, the waveform of the driving voltage VD63 applied to the picture element P63 in the last, namely fourth row is different from those of the driving voltages applied to the picture elements in the other rows, and the effective value of the driving voltage in the last row applied during a scanning period is lower than that in the other rows.
As described above, in display devices of the prior art, the effective values of the driving voltages in the last fourth row (e.g., VD63) are lower than those of the driving voltages in the first through third rows (e.g., VD51).
The optical transmissivity of the picture element P, namely the liquid crystal layer, changes depending on the effective value of a voltage applied. Consequently, even when the equivalent display voltage VS is applied, a driving voltage applied to the picture elements forming the last row has a lower effective value than in the other rows, and, for example, in a normally white type display panel (during no voltage application: white color image; during voltage application: black color image), the black color image in the last row becomes whiter than that in the other rows and the display quality is lowered. Such disadvantage can be eliminated when also the return circuits of the condensers in the other rows are connected to the scanning power supply voltage VGL or the counter electrode VQ like the condensers in the last row. Such connection, however, makes the wiring of the liquid crystal display panel complex and accordingly causes other problems such as reduction of area available for picture elements.
For the above reasons, in conventional liquid crystal display panels, countermeasures such that the last row of a display panel is masked, for example, 479 rows are available in a display panel with 480 rows, have been taken.
In the VGA standard employed in display panels for personal computers, however, the number of rows is defined as 480, and therefore it is problematic that the data displayed in the display panel is not sufficient when the picture elements in the last row are masked.